The present invention relates in general to substrate manufacturing technologies and in particular to methods for improving process results while etching in a plasma processing chamber.
In semiconductor fabrication, devices such as component transistors may be formed on a substrate, e.g., a semiconductor wafer or a glass panel. Above the substrate, there may be disposed a plurality of layers from which the devices may be fabricated. Metallic interconnect lines, which may be etched from a metal layer disposed above the substrate, may then be employed to couple the devices together to form the desired circuit.
In an exemplary plasma process, the wafer is coated with a layer of photoresist which is patterned in a lithographic step, and subsequently etched in a plasma step. Using appropriate etchants, such as chlorine, HBr, and fluorocarbon gases for example, areas of the certain layers (e.g., the polysilicon layer) that are unprotected by the mask are etched away, leaving behind columns and trenches that form electrical structures on the substrate. The plasma processing system further uses a technique called process endpoint detection to determine precisely when to stop the etching process. An exemplary technique is optical emission spectroscopy.
Fluorocarbon gases that are typically used in the plasma etch process can, however, cause excess lateral etching along trench walls of the photoresist layer and/or the bottom anti-reflective coating layer. The use of such etchant gases may increase the width of a trench, and therefore decreasing the width of the surrounding columns. This effect, commonly called CD bias, is normally measured as the difference in width of a specific feature after etching relative to the width just before etching. Minimizing CD bias can be critical to the manufacturing process since it directly impacts the performance and function of the resultant devices.
To facilitate discussion, FIG. 1A illustrates a cross-sectional view of a layer stack 100, representing the layers of an exemplar semiconductor IC, prior to a lithographic step. In the discussions that follow, terms such as “above” and “below,” which may be employed herein to discuss the spatial relationship among the layers, may, but need not always, denote a direct contact between the layers involved. It should be noted that other additional layers above, below, or between the layers shown may be present. Further, not all of the shown layers need necessarily be present and some or all may be substituted by other different layers.
At the bottom of layer stack 100, there is shown a nitrodized oxide layer 108, typically comprising SiO2. Above the nitrodized oxide layer 108, there is disposed a polysilicon layer 106. Above the polysilicon layer 106, there is disposed a BARC (bottom anti-reflective coating) layer 104. The BARC layer 104 helps prevent light (e.g., from the lithography step that patterns the photoresist) from being reflected and scattered off the surface of the polysilicon layer 106. Above the BARC layer 104 is an overlaying photoresist layer 102.
Photoresist layer 102 is commonly patterned for etching through exposure to ultra-violet rays. By way of example, one such photoresist technique involves the patterning of photoresist layer 102 by exposing the photoresist material in a contact or stepper lithography system to form a mask that facilitates subsequent etching.
For illustration purposes, FIG. 1B shows a somewhat idealized cross-sectional view of layer stack 100 of FIG. 1A after photoresist layer 102a-b is has been processed through lithography. In this example, trench 112 has been removed, leaving two columns of photoresist 102a-b. Since modern IC circuits are scaled with increasingly narrower design rules to achieve greater circuit density, feature sizes (i.e., the width of the interconnect lines or trenches between adjacent interconnect lines) have steadily decreased.
FIG. 1C shows an idealized cross-sectional view of layer stack 120 of FIG. 1B after the BARC layer has been etched in the plasma system. FIG. 1D further shows an idealized cross-sectional view of layer stack 140 of FIG. 1C after the polysilicon layer has been etched in the plasma system.
As the feature sizes shrink, however, it becomes increasingly difficult to maintain the CD of the columns and trenches that form the substrate's IC components. Fluorocarbon-based etchants, although being very efficient and widely available, are often very difficult to control in plasma processing systems, causing excess vertical and/or lateral etching on the features. To counter the tendency of fluorocarbon-based etchants to over etch, it is not uncommon for mask designers to purposely distort feature dimensions on the mask in order to compensate for the over etching, consequently decreasing accuracy and increasing design complexity and cost.
In view of the foregoing, there are desired improved methods for CD control using fluorocarbon-based chemistry in a plasma process system.